Commercially available processors meet the performance and function requirements for many types of applications, but may not be sufficiently radiation hardened for certain other applications such as, for example, space applications. For example, commercial microelectronics have higher performance, function, and density compared with microelectronics designed for space applications; however, designs for such commercial microelectronics result in failure caused by Single Event Upsets (SEUs) in space applications. As is known by those of ordinary skill in the art, ionizing radiation in space (and ground) based applications directly upset storage circuits, such as SRAMs, register files and flip-flops, and can cause voltage latching glitches in combinational logic. Illustratively, SEUs may cause the circuit to perform incorrect or illegal operations such as, for example, flipping the state of a bi-stable circuit leading to complete device failure.
In space applications, the major radiation sources are high-energy protons and high-energy heavy ions (from helium up to about any heavy stable isotope). The high-energy cosmic protons and ions are known to produce secondary fragments which cause SEUs and single event latchups (SELs), as well as total failure resulting from total dose (long accumulation of radiation) in semiconductor ICs. For applications on the ground, a major source of radiation is from neutrons. These terrestrial neutrons interact with the devices and the packaging materials to produce secondary (spallation) ions that cause upsets (mainly single event upsets SEUs). The spectra of the secondary ions depend on the device back end of the line (BEOL) materials.
In current designs, the SEUs are prevented by the use of shallow trench isolation (STI) structures, which isolate and separate devices. Also, to ensure that the device does not completely fail, redundant transistors are also used. The redundancy is typically provided by electrically connecting transistors in series. However, electrically connecting transistors in series requires valuable chip space on multiple levels, in addition to complex processing steps. For example, the electrical connection between two electrical devices requires the fabrication of contacts and an upper wiring level. That is, in implementation, a dielectric layer has to be deposited over the electrical devices and patterned to form openings exposing their diffusions. A metal such as, for example, tungsten, is then deposited in the opening to form contacts with the diffusions. A metal wiring layer, on an upper layer, is then fabricated to connect the contacts. In all, these processing steps require added fabrication costs and require valuable chip space, which can otherwise be used for active components.
The STI structures may act as a barrier to minority carrier diffusion, but they typically are not dense enough due to the additional need of the contacts and wiring layer. Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.